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Posted by swlem3 on July 23, 2023 at 19:33:19.
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Could someone give me a little help with the e-probe schematic attached to this link? www.dropbox.com/scl/fi/06euw67ka8l1xnos1apsp/modifiedeprobe.pdf?rlkey=03h3y83sn53w70m0ua7anxu36&dl=0 My question concerns the 50k pot in the diagram. It's function appears to vary the dc bias on the gate of the FET. What would be the proper bench setup to optimize the setting of said pot? What does changing the bias voltage do to need careful adjustment? The originator of this schematic seems unavailable for contact, so I'm asking on this forum. Ray
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